The present invention relates to a method and/or architecture for an embedded memory generally and, more particularly, to an address input circuit for a memory block.
Embedded memory is used for a variety of logic functions in programmable logic devices. The logic function varieties require the embedded memory to operate in one of several modes as selected by a user. For example, the embedded memory must operate in an asynchronous mode to implement lookup tables. In another example, the embedded memory must operate in a synchronous mode to implement a pipelined data storage function.
The embedded memory has an asynchronous core memory block in order to operate in the asynchronous mode. Operation in other modes requires additional circuitry connected to the inputs of the memory block to perform a desired logic function. For example, a dedicated counter is implemented to allow the memory block to be accessed in a sequential or burst mode. A separate input register is implemented to provide for synchronous input operations. As a result, considerable area is consumed by the additional circuitry and one or more registers required to make the embedded memory flexible.
The present invention concerns a circuit having an address circuit and a memory. The address circuit may be configured to (i) receive an address as a parallel input signal and as a serial input signal, (ii) present the address as an output address in one of an asynchronous mode, a synchronous mode, and a shift mode, and (iii) change the second address by one unit in a counter mode. The memory may be configured to receive the output address.
The objects, features and advantages of the present invention include providing an address input circuit to a memory block that may (i) access the memory block in an asynchronous, synchronous, counter, and shift mode, (ii) require only one register per address bit, (iii) provide for sequential configuration of data within the memory block, and/or (iv) support scan operations to verify proper operation of the registers.